Handshake Solutions [1] is a business line of the Philips Technology Incubator that has developed a design flow that enables a fast path to exploit the benefits from self-timed circuits, such as ultra-low power consumption and reduced electromagnetic emission. The quick route is enabled by the combination of two elements: a high-level “timeless” design language and an intermediate architecture based on handshake circuits.
The design language, Haste, offers a syntax similar to behavioral Verilog, and in addition has explicit constructs for parallelism, communication, and hardware sharing. Haste is a behavioral language in the sense that it supports sequential composition of actions (such as assignments and communications) without reference to their timing, and also allows for data-dependent while-loops and other data-dependent execution traces. As a parallel programming language, Haste supports CSP concepts such as synchronized channel communication, both via point-to-point channels and through broadcast and narrowcast channels. In addition, Haste also allows for the design of interfaces and protocols through its support of synthesizable edge/posedge/negedge (wait for event) and wait (for state) constructs.
Designers experience and have reported high productivity in Haste. It turns out that compared to synthesizable VHDL the number of code lines is more than halved, thus facilitating design-space exploration and re-use, and improving design productivity. Starting from Haste, one can compile to behavioral Verilog for functional verification, to clock-gated circuits for mapping onto FPGAs, and to clockless circuits for ultra-low-power and low-EME VLSI implementations. This compilation exploits an intermediate architecture based on handshake components, which implement language constructs of Haste using handshake protocols. Handshake components and circuits support a modular design style, and can easily be implemented both as a clocked and as a self-timed circuit.
The Handshake Solutions design flow is complementary to and compatible with third party EDA tools, e.g. for logic synthesis, test-pattern generation, and placement and routing. The clockless design flow works with standard-cell libraries, does not need any special cells and has a scan-test solution implemented.
The talk will highlight the expressive power of Haste, how it is implemented in handshake circuits, and how this has led to concrete IC designs on the market.